<div class="content-intro">Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here. </div>The work You will represent the Architecture function in Ambiq’s Singapore development office and serve as the primary architectural guide for the site’s engineering team. Your focus is the SoC’s peripheral subsystems — audio, imaging and display, and high- and low-speed interfaces — architected for the power budgets of battery-powered wearables and IoT devices. On a sub-threshold SoC, external interfaces frequently dominate the power budget, so decisions that are routine elsewhere (when a link wakes, what stays retained, how data moves without waking the CPU) become first-order architectural problems. These subsystems live on both sides of the package, and so does this role. Defining them properly requires fluency beyond the pins: cable and connector requirements, board-level electrical constraints, PHY behavior, and the driver model on the far side of the interface. A USB mode definition that ignores cable power delivery or the host driver stack is wrong before tape-out. You will be expected to reason across that whole span — and to deliver it as silicon architecture. What you’ll own Ordered by how you’ll spend your time — the silicon lifecycle runs through all of it. <ul> <li>Architecture specifications for the SoC’s peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode — the documents RTL design and verification teams implement from</li> <li>Off-die interface definition — modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model</li> <li>Debug at RTL and gate level with the design team when implementation raises questions the specification must answer</li> <li>Partnership with physical design to ensure robust, optimal implementation of what you specify</li> <li>Power and performance trade-off analysis across full system dataflows — die, package, board, and software — guiding both hardware and software development</li> <li>IP investigation, assessment, and selection — build-vs-license recommendations with the analysis to

HW System/SoC Architect

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