Staff PCB Design Engineer/Layout Engineer, Air Dominance and Strike

<div class="content-intro"><p>Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</p></div><p> </p> <div> <p><strong>ABOUT THE JOB</strong></p> <p><strong> </strong><br>We are looking for an <strong> Staff PCB Designer / Staff Layout Engineer </strong>to join our rapidly growing team in <strong>Costa Mesa, CA</strong>. In this role, you will work closely with avionics, system, and software engineers to create test systems for development, qualification, verification, and validation purposes. If you are someone who thrives in a fast-paced environment supporting new developments, active deployments, and customer operated hardware, we are looking for you.</p> <br>REQUIRED QUALIFICATIONS</div> <ul> <li>10+ years of experience with PCB layout</li> <li>5+ years of experience with Altium</li> <li>Ability to read and interpret schematics, apply best practices appropriate for each design, and push back on schematic or architectural decisions that create layout, manufacturability, or integrity risk</li> <li>Deep understanding of PCB fabrication and assembly processes, limitations, design rules, and best practices, including the ability to define and validate stackups with fabricators</li> <li>Experience owning ECAD libraries and library standards — footprint creation and verification, IPC compliance, and governance across multiple designers</li> <li>Working knowledge of signal and power integrity principles, including the ability to interpret SI/PI simulation results and translate them into layout constraints</li> <li>Expert-level high speed digital layout and controlled impedance routing — DDR, PCIe, SerDes, Ethernet, USB — including length/skew matching, differential pair routing, and return path management</li> <li>Experience with high density designs: fine-pitch BGA fanout, HDI/microvia construction, and stackups greater than 12 layers</li> <li>Demonstrated technical leadership: serving as lead designer on complex or multi-board programs, setting and documenting layout constraints, conducting design reviews, and mentoring less experienced designers</li> <li>Ability to manage layout scope, schedule, and risk across concurrent programs while collaborating with electrical, mechanical, and program teams</li> <li>Eligible for security clearance</li> </ul> <div>PREFERRED QUALIFICATIONS</div> <ul> <li>CID+, CID++ and/or PCEA-CPCD certification</li> <li>Working experience applying MIL-STD and IPC standards, including IPC-2221/2222, IPC-6012 Class 3, and IPC-A-610</li> <li>Experience with rigid-flex, RF/mixed-signal, and thermally constrained designs</li> <li>Experience designing and analyzing power distribution networks using SI/PI tools (HyperLynx, Ansys SIwave, Cadence Sigrity, or equivalent)</li> <li>Advanced Altium proficiency: constraint/rule management, scripting or automation, Altium 365/Concord Pro, and version-controlled design data</li> <li>Experience leading DFM/DFA engagement with fab and ass