Principal Analog Mixed-Signal Design Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p></p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Role Overview</h2> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers.</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.</p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Key Responsibilities</h2> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Analog & Mixed-Signal Design</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Silicon Execution & Validation</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Define and execute test plans to correlate silico