Principal IP Signoff & Methodology Engineer
Job Description
<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 3">Role Overview</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":281,"335559739":281}"> </span></p> <p><span data-contrast="auto">Astera Labs is looking for a </span><strong><span data-contrast="auto">Principal</span></strong><strong><span data-contrast="auto"> IP Signoff & Methodology</span></strong><span data-contrast="auto"> </span><strong><span data-contrast="auto">Engineer </span></strong><span data-contrast="auto">to own the readiness, quality, and signoff of internal and external IP blocks before they are released into SoC and system implementation flows. This role sits at the intersection of IP development, physical design, and tapeout execution, with responsibility for ensuring that IP deliverables from both external vendors and internal engineering teams are complete, validated, and integration-ready.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><span data-contrast="auto">You will drive signoff closure and revision management across key IP handoff views and verification checks, including RTL, SDC, LEF/DEF, netlists, timing, physical verification, and package-aware considerations such as die and bump views. You will also drive configuration management of digital IP and ensure adherence to Astera-defined specifications, configurations, and usage profiles. The right candidate combines strong digital and physical design fundamentals with disciplined execution, debug ownership, and the ability to partner closely across digital, analog, package, CAD, and integration teams.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p> </p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">Key Responsibilities:</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":299,"335559739":299}"> </span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 3">IP Release Readiness</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":281,"335559739":281}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"3355