Principal Physical Design Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p></p> <p><strong>Role Overview </strong></p> <p>Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters — driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market. </p> <p>This is a hands-on technical leadership role. You will architect physical design methodology, mentor senior engineers, and partner closely with RTL, DFT, analog, and package teams to take our next generation of connectivity silicon from RTL to tapeout on leading-edge nodes. </p> <p><strong>Key Responsibilities </strong></p> <ul> <li>End-to-End RTL2GDS Ownership </li> <li>Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera's connectivity product portfolio </li> <li>Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs </li> <li>Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets </li> <li>Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab </li> <li>Timing, Power & Signoff </li> <li>Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff </li> <li>Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure </li> <li>Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around </li> <li>Technical Leadership & Cross-Functional Partnership </li> <li>Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies </li> <li>Establish and evolve physical design methodology, scripts, and flows across the team </li> <li>Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions </li> </ul> <p><strong>Basic Qualifications </strong></p> <ul> <li>Bachelor's degree in Electrical Engineering, Computer Engineering, or related field </li> <li>8+ years of physical design experience with multiple tapeouts on advance