Principal Physical Design Engineer, Methodology

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><span data-contrast="auto">Role Overview</span></strong><span data-ccp-props="{"201341983":0,"335559739":200,"335559740":276}"> </span></p> <p><span data-contrast="auto">As a </span><strong><span data-contrast="auto">Principal Physical Design Engineer - Methodology</span></strong><span data-contrast="auto">, you will define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts. This role is fully on-site at our San Jose, CA location.</span><span data-ccp-props="{"201341983":0,"335559739":200,"335559740":276}"> </span></p> <p><strong><span data-contrast="auto">Key Responsibilities:</span></strong></p> <ul> <li class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Flow & Methodology Ownership</strong> <ul> <li>Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR</li> <li>Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)</li> <li>Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability</li> <li>Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements</li> </ul> </li> <li class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Automation & Scale</strong> <ul> <li>Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage</li> <li>Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs</li> <li>Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization</li> </ul> </li> <li><strong>Standards, Quality & Enablement</strong> <ul> <li>Establish best practices, runset standards, and quality checks th