Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><u>Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:</u></strong></p> <p><strong>Role Overview</strong> </p> <p>We are seeking an experienced <strong>Principal / Senior Principal Design Verification Engineer</strong> to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success. </p> <p>The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges. </p> <p><strong>Key Responsibilities</strong> </p> <p><strong>Technical Leadership</strong> </p> <ul> <li>Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon. </li> </ul> <ul> <li>Define verification methodologies, reusable verification frameworks, and best practices across multiple programs. </li> </ul> <ul> <li>Drive verification planning, execution, coverage closure, and sign-off. </li> </ul> <ul> <li>Identify verification risks early and proactively drive mitigation plans. </li> </ul> <ul> <li>Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews. </li> </ul> <p><strong>Design Verification</strong> </p> <ul> <li>Architect and develop scalable UVM/System Verilog verification environments. </li> </ul> <ul> <li>Develop constrained-random, coverage-driven verification methodologies. </li> </ul> <ul> <li>Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models. </li> </ul> <ul> <li>Debug complex RTL, protocol, timing, and integration issues. </li> </ul> <ul> <li>Drive regression planning, automation, and continuous integration improvements. </li> </ul> <ul> <li>Develop reusable VIP and verification infrastructure across multiple product lines. </li> </ul> <p><strong>Protocol Verification</strong> </p&g