<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div> About the Role We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes Key Responsibilities <ul> <li> Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes. </li> <li> Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence. </li> <li> Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis. </li> <li> Work on key physical design areas including: <ul> <li> EM/IR analysis and power grid optimization </li> <li> Congestion analysis and mitigation </li> <li> Clock skew optimization and clock quality improvement </li> <li> RC extraction-aware placement and routing </li> </ul> </li> <li> Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. </li> <li> Support floorplan development and chip partitioning for high-speed transceiver designs. </li> <li> Perform ECO implementation and assist with tapeout signoff activities. </li> <li> Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools. </li> <li> Use industry-standard tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre for implementation and signoff. </li> <li> Develop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity. </li> </ul> Required Qualifications <ul> <li> Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field. </li> <li> 5+ years of experience in physical design, preferably with advanced technology nodes. </li> <li> Strong experience with: <ul> <li> Floorplanning, plac

Senior Engineer PD

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