<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <h1 class="PDq2pG_selectionAnchorContainer" data-section-id="l2rpfr" data-start="0" data-end="39">Senior STA Engineer – Job Description</h1> <p data-start="41" data-end="163"><strong data-start="41" data-end="54">Position:</strong> Senior STA Engineer<br data-start="74" data-end="77"><strong data-start="77" data-end="92">Experience:</strong> 6+ years<br data-start="103" data-end="106"><strong data-start="106" data-end="119">Location:</strong> Ahmedabad<br data-start="130" data-end="133"><strong data-start="133" data-end="153">Employment Type:</strong> Full-time</p> <h3 data-section-id="1gkutcd" data-start="165" data-end="180">Job Summary</h3> <p data-start="181" data-end="519">We are looking for a <strong data-start="202" data-end="225">Senior STA Engineer</strong> with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.</p> <h3 data-section-id="164ueu3" data-start="521" data-end="545">Key Responsibilities</h3> <ul data-start="546" data-end="1999"> <li data-section-id="1r7x2uk" data-start="546" data-end="642">Own <strong data-start="552" data-end="578">STA and timing signoff</strong> activities from synthesis through physical design and tape-out.</li> <li data-section-id="177s0zq" data-start="643" data-end="720">Perform <strong data-start="653" data-end="682">MCMM/MMMC timing analysis</strong> across all functional and test modes.</li> <li data-section-id="17vnu9f" data-start="721" data-end="815">Analyze and debug <strong data-start="741" data-end="814">setup, hold, recovery, removal, min/max, and clock-related violations</strong>.</li> <li data-section-id="1ai3568" data-start="816" data-end="970">Develop, review, and validate <strong data-start="848" data-end="867">SDC constraints</strong>, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.</li> <li data-section-id="bevsbq" data-start="971" data-end="1102">Perform detailed <strong data-start="990" data-end="1030">clock tree and clock timing analysis</strong>, including skew, latency, uncertainty, jitter, and clock reconvergence.</li> <li data-section-id="168a4rc" data-start="1103" data-end="1199">Drive <strong data-start="1111" data-end="1129">timing closure</str