SoC Design Director

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. </p> <p><strong> </strong> </p> <p><strong>Key Responsibilities:</strong> </p> <ul> <li>Design and implement high-performance digital solutions, including RTL development and synthesis. </li> </ul> <ul> <li>Collaborate with cross-functional teams on IP integration for processor IPs and peripherals </li> </ul> <ul> <li>Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind </li> </ul> <ul> <li>Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. </li> </ul> <ul> <li>Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. </li> </ul> <ul> <li>Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows </li> </ul> <ul> <li><strong> </strong> </li> </ul> <p><strong>Basic Qualifications / Experience Level:</strong> </p> <ul> <li>Bachelor’s in Electronics/Electrical engineering (Master's preferred). </li> </ul> <ul> <li>Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation. </li> </ul> <ul> <li>Proven expertise in RTL development, synthesis, and timing closure. </li> </ul> <ul> <li>Experience with front-end design, gate-level simulations, and design verification. </li> </ul> <ul> <li>Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. </li> </ul> <p><strong> </strong> </p> <p><strong>Required Expertise:</strong> </p> <ul> <li>Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes (< 16nm) </li> </ul> <ul> <li>Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles .</li> </ul> <ul> <li>Hands-on experienc