Soc Design Verification Director

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <p></p> <h2>Job Title: Director of SoC Design Verification</h2> <h3>Overview</h3> <p>We are seeking a seasoned Director of SoC Design Verification with <strong>20+ years of experience</strong> to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.</p> <h3>Key Responsibilities</h3> <ul> <li>Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.</li> <li>Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.</li> <li>Guide verification of complex SoC subsystems including <strong>HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols</strong>.</li> <li>Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.</li> <li>Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.</li> <li>Represent verification in executive reviews, customer engagements, and industry forums.</li> <li>Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.</li> </ul> <h3>Qualifications</h3> <ul> <li>Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).</li> <li><strong>20+ years of experience</strong> in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.</li> <li>Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.</li> <li>Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.</li> <li>Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.</li> </ul> <h3>Required Experience</h3> <ul> <li>Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, <strong>HSIO, and peripherals</strong>.</li>