Tech Lead Engineer, Design Verification
Job Description
<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <p><span data-contrast="none"><span data-ccp-parastyle="heading 2">Role Overview</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></p> <p><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"276295ed-5df2-5456-988c-5fdbab071054|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"180",335559738,"180",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",469775498,"Body Text",469778324,"Body Text"]}">As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p> <p><span data-contrast="auto"><span data-ccp-parastyle="Body Text">Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver </span><span data-ccp-parastyle="Body Text">highly reliable</span><span data-ccp-parastyle="Body Text"> PCIe and </span><span data-ccp-parastyle="Body Text">UALink</span><span data-ccp-parastyle="Body Text"> connectivity products that keep AI accelerators, memory, and compute resources </span><span data-ccp-parastyle="Body Text">operating</span><span data-ccp-parastyle="Body Text"> at scale.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p> <p><span data-contrast="none"><span data-ccp-parastyle="heading 2">Key Responsibilities</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469