Tech Lead, Formal Verification

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.</p> <p> </p> <p><strong>Key Responsibilities</strong> </p> <ul> <li>Develop comprehensive formal verification plans from architecture and design specifications by identifying critical design properties, protocol requirements, and micro-architectural invariants.</li> <li>Develop and execute formal verification environments, assertions, properties, and checkers.</li> <li>Drive proof convergence through advanced abstraction and complexity reduction techniques.</li> <li>Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.</li> <li>Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.</li> <li>Improve verification productivity through reusable methodologies, automation, and best practices.</li> <li>Ensure comprehensive design correctness and provide technical leadership and mentorship across multiple projects.</li> <li>Drive bug triage, root-cause analysis, and resolution in collaboration with cross-functional teams.</li> <li>Support project planning by estimating verification effort, tracking execution progress, identifying risks, and driving mitigation plans.</li> <li>Participate in design reviews and contribute to verification sign-off strategies and quality metrics.</li> <li>Promote assertion-driven design practices and formal verification adoption across engineering teams.</li> </ul> <p> </p> <p><strong>Required Qualifications</strong> </p> <ul> <li>Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. </li> <li>5-10 experience in semiconductor verification, including significant formal verification experience.</li> <li>Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques. </li> <li>Hands-on experience with one or more formal verificatio