Hardware Verification Engineer

<div class="content-intro"><p><strong>Baya Systems is inspired by the <a href="https://bayasystems.com/about/">baya bird</a>, also known as the <a href="https://bayasystems.com/about/">weaver</a>. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.</strong></p> <p>Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!</p></div><p class="font_8 wixui-rich-text__text"> </p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">DESIGN VERIFICATION ENGINEER</span></p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">SANTA CLARA, CA</span></p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions</span></p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Responsibilities​:</span></p> <ul> <li class="font_8 wixui-rich-text__text">Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems</li> </ul> <ul class="font_8 wixui-rich-text__text"> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Collaborate with software teams to define and implement configurable testbenches</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Work with design teams test plans, failure debug, coverage, etc.</span>​</p> </li> </ul> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Qualifications and Preferred Skills​</span></p> <ul class="font_8 wixui-rich-text__text"> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">BS, MS in </span><span class="wixui-rich-text__text">Electrical Engineering</span><span class="wixui-rich-text__text">, Computer </span><span class="wixui-rich-text__text">Engineering</span><span class="wixui-rich-text__text"> or </span><span class="wixui-rich-text__text">Computer </span><span class="wixui-rich-text__text">Science</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_